The present invention relates to a central processing unit and an arithmetic unit and is favorably used for protection against a power analysis attack, for example.
The power analysis attack analyzes a slight bias of the power consumption dependent on data processed in a central processing unit (CPU) to acquire confidential information processed in the CPU (e.g., see non-patent documents 1 through 3).
Japanese Unexamined Patent Publication No. 2011-234312 (patent document 1) discloses a well-known technology capable of improving the resistance to power analysis attack. The technology can improve the resistance to power analysis attack without greatly redesigning a CPU (especially an arithmetic unit) of the related art. The inventors of this application invented this technology.
Specifically, the arithmetic unit described in the document is provided with a selection circuit uniquely corresponding to at least part of circuit elements such as logical gates and flip-flops configuring the arithmetic unit. Each selection circuit receives an output signal from the corresponding circuit element and a signal irrelevant to arithmetic operations and selectively outputs one of the signals. This can change internal signals of the arithmetic unit and output signals from the same to states irrelevant to arithmetic operations.    Patent Document 1: Japanese Unexamined Patent Publication No. 2011-234312    Non-Patent Document 1: Kocher, et al., “Differential Power Analysis.” CRYPTO 1999. LNCS, vol. 1666, Springer, Heidelberg (1999). pp. 388-397.    Non-Patent Document 2: Brier, et al., “Correlation Power Analysis with a Leakage Model.” CHES 2004.LNCS, vol. 3156, Springer, Heidelberg (2004), pp. 16-29.    Non-Patent Document 3: Suzuki, et al., “DPA Leakage Models for CMOS Logic Circuits.” CHES 2005. LNCS, vol. 3659, Springer-Verlag (2005), pp. 366-382.